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Top-level
 so here's the solution: all the signals in the MCA bus domain go to a latch clocked in that domain (the first "always" block). then *without any combinational logic* the output of that latch goes *directly* to another latch (the second "always" block) located in the main clock domain. (i have another flip flop in main clock domain just for detecting the edge) 32 comments
so how does this compare with the real drive? it transfers a word in about 1.6us (compared to 2us for mine), so it is slightly faster for sustained data transfer with data that fits in the internal buffer. however, seek times (in the ms range) more or less cancel this out.  @tubetime Nice! (And LOLing because I JUST asked a client whether they really need the big teensy or could they go with the smaller one.)   @tubetime hey @azonenberg weren’t you looking for examples of probes changing behavior of the DUT?  @tubetime A coincidence that DBB6 == 6DDB << 1 ? Could it be slipping a bit?  @tubetime Ugh, that's NEVER good. I see lots of oscilloscope probing in your future. @tubetime Why is there a SD Card slot forseen on the baseboard as well? @1000millimeter in case i want to use a soft CPU core in the FPGA instead of a separate Teensy |
Gregory's Server
next step is to optimize the interface speed. right now it takes 25us to read a sector from the SD card but ~5 milliseconds (ouch) to DMA it to the PC!
it's mostly an issue with the Teensy-to-FPGA interface, which is async and simple: 4 address lines, 16 data lines, a read control line, and a write control line. everything else is done as a register in the 4-bit address space. flag register for status and mailbox sync bits.