huh, once I connect the logic analyzer, the problem...

huh, once I connect the logic analyzer, the problem takes much longer to reproduce; the probability of data corruption drops dramatically. interesting but it makes things much harder to debug.

Like 17 Nov 2023 at 23:59 | Open on mastodon.social

8 comments

/dev/rdsk/c5t1d0s2 replied to Tube🍂Time

@tubetime hey @azonenberg weren’t you looking for examples of probes changing behavior of the DUT?

18 Nov 2023 at 0:04 | Open on aus.social

Tube🍂Time replied to Tube🍂Time

looks like it is skipping a transfer here somehow. it transfers B66D, then it skips 6DDB and goes to DBB6. the preempt line seems to deassert right before arb/gnt goes high. that doesn't seem right.

18 Nov 2023 at 0:33 | Open on mastodon.social

Jon Dubovsky replied to Tube🍂Time

@tubetime A coincidence that DBB6 == 6DDB << 1 ? Could it be slipping a bit?

18 Nov 2023 at 0:37 | Open on mastodon.social

Tube🍂Time replied to Jon

@jond no that is just the pattern in the disk image. presumably a disk area that was never written to after being formatted and still contains this bit pattern.

18 Nov 2023 at 1:15 | Open on mastodon.social

Tube🍂Time replied to Tube🍂Time

the smoking gun: an invalid bus transfer. both rd and wr are asserted at the same time. before that we see the missing data on the bus: 6DDB. so the card thinks it is in a DMA cycle even though it is not, and it's putting data on the bus when it shouldn't be!