Gregory's Server
the smoking gun: an invalid bus transfer. both rd and wr are asserted at the same time. before that we see the missing data on the bus: 6DDB. so the card thinks it is in a DMA cycle even though it is not, and it's putting data on the bus when it shouldn't be!
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2 comments
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i deleted 3 characters from my verilog and it works now. 😅
(i still need to test writes, and i need to test it without the logic analyzer card)