Gregory's Serverlooks like it is skipping a transfer here somehow. it transfers B66D, then it skips 6DDB and goes to DBB6. the preempt line seems to deassert right before arb/gnt goes high. that doesn't seem right.
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5 comments
 @jond no that is just the pattern in the disk image. presumably a disk area that was never written to after being formatted and still contains this bit pattern. the smoking gun: an invalid bus transfer. both rd and wr are asserted at the same time. before that we see the missing data on the bus: 6DDB. so the card thinks it is in a DMA cycle even though it is not, and it's putting data on the bus when it shouldn't be! i deleted 3 characters from my verilog and it works now. 😅 (i still need to test writes, and i need to test it without the logic analyzer card) @tubetime As the joke goes, its all about knowing where to tap... |
@tubetime A coincidence that DBB6 == 6DDB << 1 ? Could it be slipping a bit?