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Tube🍂Time

looks like it is skipping a transfer here somehow. it transfers B66D, then it skips 6DDB and goes to DBB6. the preempt line seems to deassert right before arb/gnt goes high. that doesn't seem right.
18 Nov 2023 at 0:33 | Open on mastodon.social
5 comments
Jon Dubovsky replied to Tube🍂Time

@tubetime A coincidence that DBB6 == 6DDB << 1 ? Could it be slipping a bit?

18 Nov 2023 at 0:37 | Open on mastodon.social
Tube🍂Time replied to Jon

@jond no that is just the pattern in the disk image. presumably a disk area that was never written to after being formatted and still contains this bit pattern.

18 Nov 2023 at 1:15 | Open on mastodon.social
Tube🍂Time replied to Tube🍂Time

the smoking gun: an invalid bus transfer. both rd and wr are asserted at the same time. before that we see the missing data on the bus: 6DDB. so the card thinks it is in a DMA cycle even though it is not, and it's putting data on the bus when it shouldn't be!
18 Nov 2023 at 1:14 | Open on mastodon.social
Tube🍂Time replied to Tube🍂Time

i deleted 3 characters from my verilog and it works now. 😅

(i still need to test writes, and i need to test it without the logic analyzer card)
28 Nov 2023 at 3:04 | Open on mastodon.social
Eric Carroll replied to Tube🍂Time

@tubetime As the joke goes, its all about knowing where to tap...

28 Nov 2023 at 4:03 | Open on mastodon.acm.org
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