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Tube❄️Time

well that was a bit tricky, but it's more or less laid out now.

17 comments
Mike Grusin replied to Tube❄️Time

@tubetime Nice! (And LOLing because I JUST asked a client whether they really need the big teensy or could they go with the smaller one.)

doragasu replied to Tube❄️Time

@tubetime Reading the silk screen of your boards is always so much fun! 😂

Tube❄️Time replied to Tube❄️Time

looks like there's a rare problem when reading sectors, around 1 in 100,000 reads. ugh these can be hard to track down

Tube❄️Time replied to Tube❄️Time

i thought it might be a timing issue caused by disabling USB debugging, but it still happens (with roughly the same statistics) with USB debugging turned on.

Tube❄️Time replied to Tube❄️Time

looks like some individual data bits are getting flipped. what's really odd is that it is repeatable and it seems to be the same bits at the same addresses.

Tube❄️Time replied to Tube❄️Time

also -- there seem to be two overlapping bugs. one causes a few bits to be corrupted for single sector reads, the other causes an entire sector's data to be shifted by several bytes.

Tube❄️Time replied to Tube❄️Time

huh, once I connect the logic analyzer, the problem takes much longer to reproduce; the probability of data corruption drops dramatically. interesting but it makes things much harder to debug.

Joel Michael replied to Tube❄️Time

@tubetime hey @azonenberg weren’t you looking for examples of probes changing behavior of the DUT?

Tube❄️Time replied to Tube❄️Time

looks like it is skipping a transfer here somehow. it transfers B66D, then it skips 6DDB and goes to DBB6. the preempt line seems to deassert right before arb/gnt goes high. that doesn't seem right.

Jon Dubovsky replied to Tube❄️Time

@tubetime A coincidence that DBB6 == 6DDB << 1 ? Could it be slipping a bit?

Tube❄️Time replied to Jon

@jond no that is just the pattern in the disk image. presumably a disk area that was never written to after being formatted and still contains this bit pattern.

Tube❄️Time replied to Tube❄️Time

the smoking gun: an invalid bus transfer. both rd and wr are asserted at the same time. before that we see the missing data on the bus: 6DDB. so the card thinks it is in a DMA cycle even though it is not, and it's putting data on the bus when it shouldn't be!

Tube❄️Time replied to Tube❄️Time

i deleted 3 characters from my verilog and it works now. 😅

(i still need to test writes, and i need to test it without the logic analyzer card)

Eric Carroll replied to Tube❄️Time

@tubetime As the joke goes, its all about knowing where to tap...

Michael Kohne replied to Tube❄️Time

@tubetime Ugh, that's NEVER good. I see lots of oscilloscope probing in your future.

Tom replied to Tube❄️Time

@tubetime I like your part naming convention! 😅

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