Gregory's Serverhere's a DMA cycle for the real hard drive. it's using the bus more efficiently, requesting a new transfer as soon as the transfer completes. my design waits for the full DMA cycle to end before requesting a new one.
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25 comments
  @tubetime Nice! (And LOLing because I JUST asked a client whether they really need the big teensy or could they go with the smaller one.)   @tubetime hey @azonenberg weren’t you looking for examples of probes changing behavior of the DUT?  @tubetime A coincidence that DBB6 == 6DDB << 1 ? Could it be slipping a bit?  @tubetime Ugh, that's NEVER good. I see lots of oscilloscope probing in your future. @tubetime Why is there a SD Card slot forseen on the baseboard as well? @1000millimeter in case i want to use a soft CPU core in the FPGA instead of a separate Teensy |
maybe theoretical maximum transfer rates would make the comparison easier:
My drive: ~1MB/s
stock HDD: ~1.25MB/s (neglecting seek)
if i put in a bunch of work and implemented burst mode DMA transfer, i might be able to hit 4.5MB/s.