got rid of some delays and now we're down to 6us per word. but there are some unexpected wide gaps in between transfers between the FPGA and the Teensy.
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got rid of some delays and now we're down to 6us per word. but there are some unexpected wide gaps in between transfers between the FPGA and the Teensy. 29 comments
so how does this compare with the real drive? it transfers a word in about 1.6us (compared to 2us for mine), so it is slightly faster for sustained data transfer with data that fits in the internal buffer. however, seek times (in the ms range) more or less cancel this out. @tubetime Nice! (And LOLing because I JUST asked a client whether they really need the big teensy or could they go with the smaller one.) @tubetime hey @azonenberg weren’t you looking for examples of probes changing behavior of the DUT? @tubetime A coincidence that DBB6 == 6DDB << 1 ? Could it be slipping a bit? @tubetime Ugh, that's NEVER good. I see lots of oscilloscope probing in your future. @tubetime Why is there a SD Card slot forseen on the baseboard as well? @1000millimeter in case i want to use a soft CPU core in the FPGA instead of a separate Teensy |
ahh that must be the issue, when i change from a read to a write, i have to set the port direction for 16 IO pins. pinMode is uhh not quick, so let's try writing to the port direction register directly.