Gregory's Server|
30 comments
 there's also some corroded vias. oh yeah and i think someone exposed this board to a lot of heat since the label on the flash memory chip has bubbled up like a matzah. anyway, i've plugged in a Pentium 90. it should be fine at 99MHz. i don't have the right heat sink so i bent up a section of music wire to hold this junk box heat sink in place. will it work? all right, i'm very suspicious of the soldering job on this clock oscillator. the upper right pin is the oscillator output and it looks like it may not be connected. boom! that did the trick! except now the floppy drive isn't working so i can't put in the reference disk 🙃 floppy drive issue seems to be this leaky electrolytic capacitor. it was working before, so i guess it must have been slowly degrading. ugh. i have this same issue with another Type 4 complex I have (486DX2-66). this is probably logic analyzer time now :blobsweats:  @tubetime logic analyser time is always a good time! 😅 Best of luck, tho! <3 here we are again, logic analyzer cables snaking out all over the place. with the *working* older type 2 complex, floppy drive read operations begin DMA by trying to negotiate arbitration level 2 on the bus (see ARB0, 1, 2, and 3). but with the *nonworking* type 4 complex, the floppy read operation begins by trying to negotiate DMA arbitration level 0! huh, the floppy controller is supposed to be hard wired to level 2. this is definitely a problem. the floppy controller chip (upper left) doesn't natively support MCA bus, so the chip in the middle (U26) implements that for it. Specifically, U26 uses an external open-drain buffer (U37, bottom) to drive the ARB lines. but it *senses* those same ARB lines with 4 separate pins. [most likely U26 is a semicustom gate array with a limited number of possible open-drain outputs] the complexity comes from the arbitration logic. it's like an open-drain priority bus, so the lowest binary value on the bus "wins" and the expected output matches the value on the bus. my theory is that for some reason, U26 (85F0464) isn't working correctly and is driving 0 onto the arbitration bus when it means to drive 2. so it thinks that it has lost arbitration, but it actually won it. then it hangs in a halfway state, and the DMA controller throws the timeout error (presumably by asserting NMI). so i can confirm this by disabling the output driver (pin 12 of U37) for ARB1, which will allow it to remain high, so U26 will drive a 2 on the bus instead of a 0. a little soldering work and a small piece of kapton tape, and i think we are ready. and the logic analyzer confirms that, with this mod, we're seeing a 2 on the bus even though U26 is bugging and trying to drive a 0. ohh yeah, 90MHz! well, technically, 99MHz (the oscillator is 66MHz instead of 60MHz).  strangely enough, when i connect my other type 4 complex (a 486DX2-66), i get the same DMA timeout error, so this "fix" is definitely a hack and doesn't really fix the root cause. (i've already disconnected all the logic analyzer cables, so i'll have to look at it some other time.) @tubetime always felt weird that even on IBM hardware that supports it, that OS/2 cant do an ACPI soft shutdown. Even OS/2 4.52  @tubetime Half a warped OS... The whole IBM fumbling the Star Trek thing with OS/2 and the Warp name silliness was pretty amusing. @tubetime I like that as a concept. Simple and elegant without any state machine complexity. |
whoever did the bodge wire also replaced the clock oscillator, changing from 60MHz to 66MHz.