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Tube🍂Time

ugh. i have this same issue with another Type 4 complex I have (486DX2-66). this is probably logic analyzer time now :blobsweats:

21 comments
Vito Sartori replied to Tube🍂Time

@tubetime logic analyser time is always a good time! 😅 Best of luck, tho! <3

Tube🍂Time replied to Tube🍂Time

here we are again, logic analyzer cables snaking out all over the place.

Tube🍂Time replied to Tube🍂Time

with the *working* older type 2 complex, floppy drive read operations begin DMA by trying to negotiate arbitration level 2 on the bus (see ARB0, 1, 2, and 3).

Tube🍂Time replied to Tube🍂Time

but with the *nonworking* type 4 complex, the floppy read operation begins by trying to negotiate DMA arbitration level 0! huh, the floppy controller is supposed to be hard wired to level 2. this is definitely a problem.

Tube🍂Time replied to Tube🍂Time

the floppy controller chip (upper left) doesn't natively support MCA bus, so the chip in the middle (U26) implements that for it. Specifically, U26 uses an external open-drain buffer (U37, bottom) to drive the ARB lines. but it *senses* those same ARB lines with 4 separate pins.

[most likely U26 is a semicustom gate array with a limited number of possible open-drain outputs]

Tube🍂Time replied to Tube🍂Time

the complexity comes from the arbitration logic. it's like an open-drain priority bus, so the lowest binary value on the bus "wins" and the expected output matches the value on the bus.

Tube🍂Time replied to Tube🍂Time

my theory is that for some reason, U26 (85F0464) isn't working correctly and is driving 0 onto the arbitration bus when it means to drive 2. so it thinks that it has lost arbitration, but it actually won it. then it hangs in a halfway state, and the DMA controller throws the timeout error (presumably by asserting NMI).

Tube🍂Time replied to Tube🍂Time

so i can confirm this by disabling the output driver (pin 12 of U37) for ARB1, which will allow it to remain high, so U26 will drive a 2 on the bus instead of a 0.

a little soldering work and a small piece of kapton tape, and i think we are ready.

Tube🍂Time replied to Tube🍂Time

and the logic analyzer confirms that, with this mod, we're seeing a 2 on the bus even though U26 is bugging and trying to drive a 0.

Tube🍂Time replied to Tube🍂Time

OH! it's booted off the reference disk!

Tube🍂Time replied to Tube🍂Time

ohh yeah, 90MHz! well, technically, 99MHz (the oscillator is 66MHz instead of 60MHz).

aeva replied to Tube🍂Time

@tubetime shouldn't Operating System/2 Version 3 just be OS/3

Tube🍂Time replied to Tube🍂Time

strangely enough, when i connect my other type 4 complex (a 486DX2-66), i get the same DMA timeout error, so this "fix" is definitely a hack and doesn't really fix the root cause.

Tube🍂Time replied to Tube🍂Time

(i've already disconnected all the logic analyzer cables, so i'll have to look at it some other time.)

Tube🍂Time replied to Tube🍂Time

well, that was fun--i'm glad i was able to get it to boot.

Chartreuse replied to Tube🍂Time

@tubetime always felt weird that even on IBM hardware that supports it, that OS/2 cant do an ACPI soft shutdown. Even OS/2 4.52

Darryl Ramm replied to Tube🍂Time

@tubetime Half a warped OS...

The whole IBM fumbling the Star Trek thing with OS/2 and the Warp name silliness was pretty amusing.
e.g. arstechnica.com/information-te

Chartreuse replied to Tube🍂Time

@tubetime I like that as a concept. Simple and elegant without any state machine complexity.

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