Gregory's Serverwith the *working* older type 2 complex, floppy drive read operations begin DMA by trying to negotiate arbitration level 2 on the bus (see ARB0, 1, 2, and 3).
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 the floppy controller chip (upper left) doesn't natively support MCA bus, so the chip in the middle (U26) implements that for it. Specifically, U26 uses an external open-drain buffer (U37, bottom) to drive the ARB lines. but it *senses* those same ARB lines with 4 separate pins. [most likely U26 is a semicustom gate array with a limited number of possible open-drain outputs] my theory is that for some reason, U26 (85F0464) isn't working correctly and is driving 0 onto the arbitration bus when it means to drive 2. so it thinks that it has lost arbitration, but it actually won it. then it hangs in a halfway state, and the DMA controller throws the timeout error (presumably by asserting NMI). @tubetime always felt weird that even on IBM hardware that supports it, that OS/2 cant do an ACPI soft shutdown. Even OS/2 4.52  @tubetime Half a warped OS... The whole IBM fumbling the Star Trek thing with OS/2 and the Warp name silliness was pretty amusing. @tubetime I like that as a concept. Simple and elegant without any state machine complexity. |
but with the *nonworking* type 4 complex, the floppy read operation begins by trying to negotiate DMA arbitration level 0! huh, the floppy controller is supposed to be hard wired to level 2. this is definitely a problem.