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Top-level
 the floppy controller chip (upper left) doesn't natively support MCA bus, so the chip in the middle (U26) implements that for it. Specifically, U26 uses an external open-drain buffer (U37, bottom) to drive the ARB lines. but it *senses* those same ARB lines with 4 separate pins. [most likely U26 is a semicustom gate array with a limited number of possible open-drain outputs] 15 comments
my theory is that for some reason, U26 (85F0464) isn't working correctly and is driving 0 onto the arbitration bus when it means to drive 2. so it thinks that it has lost arbitration, but it actually won it. then it hangs in a halfway state, and the DMA controller throws the timeout error (presumably by asserting NMI). so i can confirm this by disabling the output driver (pin 12 of U37) for ARB1, which will allow it to remain high, so U26 will drive a 2 on the bus instead of a 0. a little soldering work and a small piece of kapton tape, and i think we are ready. and the logic analyzer confirms that, with this mod, we're seeing a 2 on the bus even though U26 is bugging and trying to drive a 0. ohh yeah, 90MHz! well, technically, 99MHz (the oscillator is 66MHz instead of 60MHz).  strangely enough, when i connect my other type 4 complex (a 486DX2-66), i get the same DMA timeout error, so this "fix" is definitely a hack and doesn't really fix the root cause. (i've already disconnected all the logic analyzer cables, so i'll have to look at it some other time.) @tubetime always felt weird that even on IBM hardware that supports it, that OS/2 cant do an ACPI soft shutdown. Even OS/2 4.52  @tubetime Half a warped OS... The whole IBM fumbling the Star Trek thing with OS/2 and the Warp name silliness was pretty amusing. @tubetime I like that as a concept. Simple and elegant without any state machine complexity. |
Gregory's Server
the complexity comes from the arbitration logic. it's like an open-drain priority bus, so the lowest binary value on the bus "wins" and the expected output matches the value on the bus.