Gregory's ServerHere's the schematic, from the datasheet. Each stage holds the sampled voltage in a capacitor. The two clock phases push the capacitors up and down like a charge pump, dumping the charge into the next capacitor. Thus, the input signal appears at the output 256 clock cycles later.
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 The analog delay is reminiscent of the shift-register memories that Intel and others built before RAM chips were practical. The difference is that the digital shift register has an inverter at each stage to keep the signal digital, while the analog bucket brigade dumps the charge from stage to stage without amplification. https://www.righto.com/2014/12/inside-intel-1405-die-photos-of-shift.html  @kenshirriff So it's like 1 bit analog shift register ? I suppose as you have an analog signal on the input pin as you "shift" you also "re-sample" the input at the "clock frequency" you are using to shift the thing ? So it's a bit like a "256 bits analog sample FIFO" ? @gilesgoat Yes, although it doesn't make sense to discuss bits, since it is analog. It has 256 stages, so there are 256 analog samples inside the chip. Nowadays, you'd use a digital delay instead. @kenshirriff Yeah I mis-explained I meant "it's like every analog capacitor holds 1 analog bit". What I really meant was 256 STAGES. Yeah me too I don't get "how the transfer happens" and doesn't average .. there must be "some trick" .. @kenshirriff @gilesgoat  @kenshirriff i understood thats why they are not connected to ground but rather to the clock lines The previous capacitor is raised in potential with the one clock line going positve, so delivering its charge to the following capacitor is sitting at ground potential @kenshirriff I'm no circuits whiz, but: When clock phase 1 is asserted to +Vcc, the "donor" capacitor C1 will be connected to the "recipient" capacitor C2, and the voltage C2 sees across its terminals at the instant the clock is asserted is the voltage across C1, plus the clock voltage (+Vcc.) Then the voltage will try to equalize, so C1 will discharge and C2 will charge, and since Vcc is bigger than the input range, this will totally discharge C1 into C2, Crockcroft-walton generator style. @multioculate But why won't both capacitors end up at the average voltage: (V1 + V2 + Vcc)/2? @kenshirriff the "upside down" p-FET only lets the charge in the donor transistor through, and chokes off before the clock voltage can start contributing. Here's a quick and ugly Falstad sketch I made on my phone: You effectively get a constant 0.7V offset from the MOSFET threshold added to it because of my sloppy circuit, but I imagine the real one accounts for this at the input/output. |
This closeup of the die shows how the signal winds through the circuit. Each stage has two PMOS transistors and a capacitor. The horizontal metal lines provide the two clock phases and the gate voltage Vgg.