Gregory's Server@kenshirriff I'm no circuits whiz, but: When clock phase 1 is asserted to +Vcc, the "donor" capacitor C1 will be connected to the "recipient" capacitor C2, and the voltage C2 sees across its terminals at the instant the clock is asserted is the voltage across C1, plus the clock voltage (+Vcc.) Then the voltage will try to equalize, so C1 will discharge and C2 will charge, and since Vcc is bigger than the input range, this will totally discharge C1 into C2, Crockcroft-walton generator style.
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2 comments
@kenshirriff the "upside down" p-FET only lets the charge in the donor transistor through, and chokes off before the clock voltage can start contributing. Here's a quick and ugly Falstad sketch I made on my phone: You effectively get a constant 0.7V offset from the MOSFET threshold added to it because of my sloppy circuit, but I imagine the real one accounts for this at the input/output. |
@multioculate But why won't both capacitors end up at the average voltage: (V1 + V2 + Vcc)/2?