Gregory's ServerLike I'm imagining sticking an 80486 in a Mac and it notices the firmware is powerpc so it reboots into being a powerpc chip
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25 comments
 @foone Is there any reason this is useful? Like having RISCV is fun and cool, but surely this doesn't do anything practical that a pure-ARM device can't  @Gaelan I really don't know. I guess some people are looking to try risc-v? and this lets them do that without needing to buy a risc-v-only board.  @Gaelan @foone yeah. If the Risc-v side didn't function, they would blow a fuse and never tell anybody about it. If it turns out to be too buggy, they'll put out an advisory to stick with the arm personality. But if the risc-v side works and customers like it, then a future design could leave out the ARM license altogether.    @foone Is there a reason why you're only allowed to activate 2 of the 4 cores? Is it like a timing thing? @thelobdegg @foone it's only built with the connections to go between the rest of the CPU and two cores, the only difference from a regular dual-core CPU is that it can choose which two cores they could theoretically add extra of anything that's per-core and then connect all four up (and selectively disable them), but that'd be a further increase in complexity and cost (even just having the extra cores there is an increase, but presumably they think it's worth that increase) @foone it’s weird that they include 2 cores in the die that *cannot be used* (i.e. you can only use ARM XOR RISC-V) I’m so used to designs that maximize layout usage that wasting space on useless extra hardware seems heretical. I guess whichever node they’re fabbing at is cheap enough, that the die space isn’t critical.  Foone🏳️⚧️, idk but that feels kinda wasteful? But then also looking at how comparatively little die area an actual CPU core usually occupies on modern chips... 🤔 @grishka yeah I think that's the real reason they did this: they had free die space so why not?  @grishka No, no, it’s easier to do setups like the Commodore 128 when you have to use only one chip! So one of the architectures could maybe run CP/M! (The C=128 had two processors, a MOS 8502 and a Z80, and could run in three modes, one of them being CP/M on the Z80. Not sure if that kind of setup would be useful now.) Orz, interesting. I know that some consoles did a similar thing, they basically contained the entire previous-generation console either in the SoC or as a separate chip. PS2 and Game Boy Advance definitely did that. Sega Mega Drive as well, iirc. |
to explain something for anyone who hasn't read the RP2350 datasheet:
It doesn't do any code-morphing or translation or anything. The CPU is designed with 4 cores, but two slots for connecting to the rest of the CPU fabric.
So at boot it selects which two cores to power on. So it can be 2xARM or 2xRISCV or (technically!) 1xARM and 1xRISCV. There's no fancy stuff where there's a single CPU arch that can run multiple things: it's just multiple heterogynous cores.