Gregory's ServerThe chip is a gate array. A gate array starts with a generic grid of transistors. For a particular application, the transistors are wired in the metal layer to form the gates needed for a particular application. This is much cheaper than a fully-custom chip.
|
11 comments
 The chip used efficient CMOS gates, like modern chips. A CMOS gate uses two types of transistors: PMOS transistors pull the output high, while NMOS transistors pull the output low. Each "ƎE" cell has two PMOS transistors at the top and two NMOS transistors at the bottom. The chip is formed from a silicon die. Regions are doped with impurities to form the transistors. A special type of silicon called polysilicon is put on top to form the transistor gates. Two layers of metal wiring are put on top to connect everything. Wiring up the transistors in different ways produces different gates. Here, 6 transistors form a 3-input NAND gate. Metal wires provide the inputs and the output. The transistors at the top are wired in parallel, the bottom ones in series. You'd design the chip using a schematic capture program. The databook listed dozens of units that you could use, from gates to counters, adders, or registers. You'd send the design to Fujitsu, where software would layout the chip and they'd manufacture it. Around the edges of the chip, bond wires connect the chip to the external pins. Special I/O cells allow the pins to be used as inputs or outputs. These cells are much larger than the regular cells to provide the high currents necessary to communicate with the outside world. This Ethernet chip worked with another Fujitsu chip, the 8502A that did the low-level signal handling for Ethernet. I wrote about that chip in an earlier thread:  @kenshirriff does anyone archive such ancient EDA / schematic capture software? Would be interesting to see a screen recording of how they were used... #retrocomputing  @kenshirriff oh wow, back in my Uni days, I did a presentation on the semi custom chips that were available in the day. PALs, GALs, and a few more. I seem to remember that FPGAs were not among the lot in the early 80s.
[DATA EXPUNGED]
|
A disadvantage of a gate array is a lot of wasted space. The wiring channels between the transistor rows are mostly empty to provide room for the two layers of metal wiring. One layer is mostly horizontal, the other mostly vertical.