Gregory's ServerWiring up the transistors in different ways produces different gates. Here, 6 transistors form a 3-input NAND gate. Metal wires provide the inputs and the output. The transistors at the top are wired in parallel, the bottom ones in series.
|
6 comments
 Around the edges of the chip, bond wires connect the chip to the external pins. Special I/O cells allow the pins to be used as inputs or outputs. These cells are much larger than the regular cells to provide the high currents necessary to communicate with the outside world. This Ethernet chip worked with another Fujitsu chip, the 8502A that did the low-level signal handling for Ethernet. I wrote about that chip in an earlier thread:  @kenshirriff does anyone archive such ancient EDA / schematic capture software? Would be interesting to see a screen recording of how they were used... #retrocomputing  @kenshirriff oh wow, back in my Uni days, I did a presentation on the semi custom chips that were available in the day. PALs, GALs, and a few more. I seem to remember that FPGAs were not among the lot in the early 80s. |
You'd design the chip using a schematic capture program. The databook listed dozens of units that you could use, from gates to counters, adders, or registers. You'd send the design to Fujitsu, where software would layout the chip and they'd manufacture it.
http://www.bitsavers.org/components/fujitsu/_dataBooks/1989_Fujitsu_CMOS_Channeled_Gate_Arrays_Data_Book.pdf