Gregory's ServerThe most popular way of wiring computers into a network is Ethernet, invented at Xerox PARC in 1973. I looked inside a Fujitsu Ethernet chip from 1984. The silicon die has rows of transistors and metal wiring. Around the edges, bond wires connect the chip to the external pins.
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This diagram shows some of the repeated cells. The chip has a lot of flip-flops (green boxes). Red are inverters or gates, purple are TTL-to-ECL converters, yellow are weird XOR shift register stages. The chip is implemented with emitter-coupled logic (ECL). This high-speed logic family was used in mainframes and the Cray supercomputer. Although ECL was fast, it used a lot of power and wasn't very dense. ECL kind of died out as CMOS chips improved; now everything uses CMOS. ECL uses current-switching: a fixed current is switched through different paths. The bottom transistor sends a fixed current through the left or right side. It's like a differential pair in an op-amp; the transistor with the higher input voltage wins and gets most of the current. Closeup of an inverter on the die. Transistors have 3 contacts, resistors are outlined rectangles. An ECL inverter is 10 transistors vs 2 for a modern CMOS inverter. T4 is the current source, T2 and T3 steer the current, T1 buffers the output. T5-10 generate reference voltages. Zooming out, you can see a row of cells at the top and a wiring channel at the bottom to connect the cells. The chip has two layers of thin metal wiring, one layer mostly vertical and one layer mostly horizontal. Here's a flip-flop, holding one data bit. It is a complex circuit, consisting of a primary and a secondary latch, controlled by a clock signal. Each latch is one ECL circuit with two layers of current-steering transistors. One clock phase reads data, the other holds the value. This chip implements the low-level Ethernet signal processing: encoding and decoding bits into a clocked waveform, and detecting "collisions" on the network. Another more complex chip implements the Ethernet protocol and generates data packets.  @kenshirriff I saw this bit on the Cray Wikipedia page and thought, "That seems like a bad thing, actually."  @kenshirriff Out of curiosity... what are the blue boxes lower right? They're highlighted but not described. Thanks. :-) @stuartl The blue boxes on the chip are a repeated cell, but I haven't reverse-engineered that cell. It's left as an exercise for the reader :-) @kenshirriff Before Ethernet there was ALOHANet (over the air instead of over coax)! https://www.eng.hawaii.edu/about/history/alohanet/  @kenshirriff Thank you for such an interesting thread. My father worked for a company called General Automation in the 60s-early 70s. He designed mother boards. These illustrations reminded me of the large vellum sheets he would bring home to work on that looked just like these. Of course as a kid, I really didn't get what he did until I started using computers in the 80s.  @kenshirriff itβs incredible to me that back in 1984, things were already this small. I think I truly have underestimated how unfathomably tiny things are now π€― |
The chip is semi-custom, using a "standard cell" or "master-slice" approach. It is built from standardized circuitry blocks, e.g. gates or flip-flops. These cells are arranged in rows with wiring in between. It wastes a lot of space, but it's cheaper than a fully custom design.