Gregory's ServerThe chip is implemented with emitter-coupled logic (ECL). This high-speed logic family was used in mainframes and the Cray supercomputer. Although ECL was fast, it used a lot of power and wasn't very dense. ECL kind of died out as CMOS chips improved; now everything uses CMOS.
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 Closeup of an inverter on the die. Transistors have 3 contacts, resistors are outlined rectangles. An ECL inverter is 10 transistors vs 2 for a modern CMOS inverter. T4 is the current source, T2 and T3 steer the current, T1 buffers the output. T5-10 generate reference voltages. Zooming out, you can see a row of cells at the top and a wiring channel at the bottom to connect the cells. The chip has two layers of thin metal wiring, one layer mostly vertical and one layer mostly horizontal. Here's a flip-flop, holding one data bit. It is a complex circuit, consisting of a primary and a secondary latch, controlled by a clock signal. Each latch is one ECL circuit with two layers of current-steering transistors. One clock phase reads data, the other holds the value. This chip implements the low-level Ethernet signal processing: encoding and decoding bits into a clocked waveform, and detecting "collisions" on the network. Another more complex chip implements the Ethernet protocol and generates data packets.  @kenshirriff I saw this bit on the Cray Wikipedia page and thought, "That seems like a bad thing, actually." |
ECL uses current-switching: a fixed current is switched through different paths. The bottom transistor sends a fixed current through the left or right side. It's like a differential pair in an op-amp; the transistor with the higher input voltage wins and gets most of the current.