Zooming out, you can see a row of cells at the top and a wiring channel at the bottom to connect the cells. The chip has two layers of thin metal wiring, one layer mostly vertical and one layer mostly horizontal.
Top-level
Zooming out, you can see a row of cells at the top and a wiring channel at the bottom to connect the cells. The chip has two layers of thin metal wiring, one layer mostly vertical and one layer mostly horizontal. 2 comments
This chip implements the low-level Ethernet signal processing: encoding and decoding bits into a clocked waveform, and detecting "collisions" on the network. Another more complex chip implements the Ethernet protocol and generates data packets. |
Here's a flip-flop, holding one data bit. It is a complex circuit, consisting of a primary and a secondary latch, controlled by a clock signal. Each latch is one ECL circuit with two layers of current-steering transistors. One clock phase reads data, the other holds the value.