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Dan Luu

It really tickles my funny bone to see people make hardware SKUs to match arbitrary software restrictions.

It's, of course, horrible, in that it generates massive deadweight loss but, in general, I view the "cause" of the deadweight loss as the software restriction and not the hardware workaround.

A recent example is this IBM SKU that works around Oracle licensing limitations: if you have per-socket pricing, of course vendors will sell more cores per socket.

9 comments
vruz

@danluu This is like Steinway creating a piano that has a number of robotic wheels to move the piano closer to the player because Oracle makes piano seats that you can't move. Steinway also let the player play all of the octaves moving the piano sideways, left and right.

Per Vognsen

@danluu This is not really in the same category but you reminded me of the concept of weird IP workarounds. Are you familiar with ARM's workaround for Intel's AESNI patent? ARM's version broke aesdec (and aesenc) into two instructions instead of one and apparently that's enough to avoid infringement at the ISA level. But then their decoders just macro-op fuse each pair back into one macro-op equivalent to the Intel version. Almost reads like a comedy routine.

Dan Luu

@pervognsen That's great. I didn't know about that! Vaguely reminds me of Lexra's attempt to work around the SGI / MIPS patent on unaligned loads and stores (come on!).

Unclear how that one would've been resolved in court since Lexra settled to avoid the risk of the lawsuit being resolved in court.

Per Vognsen

@danluu Like with most such things I learned about both parts (the macro-op fusion and the patent infringement reason for splitting up the instructions) from @rygorous but I can't find any blog write-ups of the full story. The macro-op fusion part of the story is here: news.ycombinator.com/item?id=1

Dan Luu

An older example is when FIA imposed F1 team limits on CFD simulation time in TFLOPS * t.

Of course multiple teams paid extra for a funky CPU SKU with gimped TFLOPS numbers and ran at low clock speed (↓ memory latency in cycles) with cores disabled (↑ cache per core) to maximize CFD performance per TFLOP.

At least one person proposed a custom machine with 0 TFLOPS to work around the limit, but this was rejected as too risky because the result would be too absurd, a la en.wikipedia.org/wiki/Brabham_

An older example is when FIA imposed F1 team limits on CFD simulation time in TFLOPS * t.

Of course multiple teams paid extra for a funky CPU SKU with gimped TFLOPS numbers and ran at low clock speed (↓ memory latency in cycles) with cores disabled (↑ cache per core) to maximize CFD performance per TFLOP.

Alex Samolov

@danluu ah, tech content meets F1 content! ❤️

Are you an F1 fan?

Natanael ⚠️

@danluu github.com/jbangert/trapcc

"This is a proof by construction that the Intel MMU's fault handling mechanism is Turing complete. We have constructed an assembler that translates 'Move, Branch if Zero, Decrement' instructions to C source that sets up various processor control tables. After this code has executed, the CPU computes by attempting to fault without ever executing a single instruction."

ROTOPE~1 :yell:

@danluu @Natanael_L The org should sell "the official engineering platform of F1™️" rights, and make either the Xbox X or PS5 the standard modeling computer.

pól ó coileáin

@danluu back in 2007/8-ish at a previous job they deployed an entire extra VMware cluster to get the most out of their IBM WebSphere licences. what goes around comes around!

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