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Dan Luu

An older example is when FIA imposed F1 team limits on CFD simulation time in TFLOPS * t.

Of course multiple teams paid extra for a funky CPU SKU with gimped TFLOPS numbers and ran at low clock speed (↓ memory latency in cycles) with cores disabled (↑ cache per core) to maximize CFD performance per TFLOP.

At least one person proposed a custom machine with 0 TFLOPS to work around the limit, but this was rejected as too risky because the result would be too absurd, a la en.wikipedia.org/wiki/Brabham_

3 comments
Alex Samolov

@danluu ah, tech content meets F1 content! ❤️

Are you an F1 fan?

Natanael ⚠️

@danluu github.com/jbangert/trapcc

"This is a proof by construction that the Intel MMU's fault handling mechanism is Turing complete. We have constructed an assembler that translates 'Move, Branch if Zero, Decrement' instructions to C source that sets up various processor control tables. After this code has executed, the CPU computes by attempting to fault without ever executing a single instruction."

ROTOPE~1 :yell:

@danluu @Natanael_L The org should sell "the official engineering platform of F1™️" rights, and make either the Xbox X or PS5 the standard modeling computer.

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