I was puzzled by the mysterious yellow stripes on the chip. Most of the circuitry was standard NMOS: the purple-gray silicon with reddish polysilicon on top providing wiring and creating the transistor gates. But the yellow stripes were something new. 2/11

Silicon-on-sapphire got its start in 1963. Instead of starting with a silicon wafer, silicon circuits are built on top of a synthetic sapphire base. The sapphire provides insulation between the transistors, improving performance and making the chip resistant to radiation. 2/9

@kenshirriff in the 90s, when i was working in chip design, SoS chips were primarily used for military and space applications as they are much more resilient to radiation than silicon substrates. however that seems a tad overkill for a floppy drive. ;-)

Zooming way in on the 386 shows the transistors for two XOR gates. In red, a shift register for the chip's self-test feature contains XOR gates built from pass transistors. Yellow: prefetch queue control circuitry uses a completely different standard-cell XOR circuit. 2/9

@kenshirriff I love playing “Where’s Waldo” with designer initials! I’m wondering what that symbol is between ET and CK above the segment unit. Almost looks like a telephone.

@kenshirriff this is my favorite of the x86 line.

@kenshirriff amazing as always

@kenshirriff A barrel shifter was the first thing we had to design in our silicon design class back in the early 1990s.

While doing that, my own home computer was running a very much simpler chip (an early ARM). You can see the barrel shifter and ALU in the ARM1 in the link below. Mine was running an ARM 2 initially (and latterly was upgraded to an ARM 3), but very similar to this design.

https://hackaday.com/2015/12/21/reverse-engineering-the-arm-alu/

@kenshirriff The first microprocessor I worked with that had a barrel shifter was at my first job at #Tektronix - port the #Magnolia #workstation (#Motorola 68000) V7 #UNIX first to 68010 but a few years later to 68EC040. The '40 had the barrel shifter. Man rotations were zippy. Later for #WindRiver I ported #VxWorks RTOS to #MIPS and #PowerPC chips. PPC bitfield ops were efficiently done with a bunch of rotate with mask instructions - IMO the pinnacle, the kitchen sink of embedded instructions.

Early microprocessors such as the 8080 used a two-phase clock: when one phase is high, the other is low, with a gap between the high part of each phase. Processing moves step-by-step through the circuitry, one phase at a time. 2/11

@kenshirriff I found your account through your blog post and I'm very happy to have found it. Great write-up, super interesting. Thank you for taking the time to write this!

The registers are implemented as static RAM, using a circuit called T8 because it has 8 transistors. The basic concept is to put two inverters in a loop, so they can stay in either the 0 or the 1 state. Each inverter provides the input to the other. 2/11

@kenshirriff I’m old and, looking back, I think this was the biggest CPU news in my whole lifetime. Developers' productivity got maybe its biggest boost ever from not having to wear 16-bit shackles.

At the time, Ethernet chips usually just translated data packets into a stream of network bits, computing checksums. Intel's chip went much further: it included a coprocessor to move data between the network and memory independent of the main processor (i.e. DMA). 2/14

@kenshirriff

@kenshirriff One aerospace project I worked on used obsolete x386 uP's that were running out of stock. Rather than upgrade and recertify, they bought the mask(s) and had enough fabricated to support to EOL.

@kenshirriff I haven't skipped ahead but I'm guessing cache and Service Mode added transistors. #i386

The 8088 processor was designed at Intel Israel. This is indicated on the die as "i/IL". The Intel 8088 was selected for the IBM PC (1981), ensuring the success of the x86 architecture. The 8088 is a 16-bit chip internally but uses an 8-bit bus to reduce system cost. The 8088 is mostly the same as the 8086 but the bus control is redesigned, the prefetch queue is smaller, and there are numerous changes throughout the chip. 2/9

@kenshirriff I never knew there was a Hebrew version of the intel logo

@kenshirriff One of these may have fallen out of a plane off the coast of the Greek island Antikythera, landed on a shipwreck, and gotten all rusty.

@kenshirriff lovely!

@kenshirriff This is sooo mind boggling, but so ingenious. Thank you for sharing this

Flip-flops have many roles in the 8086. They hold the instruction and various fields. They store condition flags such as carry. They hold the microcode address and the 21-bit micro-instruction. They implement state machines for reads and writes. They manage the prefetch queue.

@kenshirriff The die shot is an aerial photo of your home town. #8086cpu

@kenshirriff @gomijacogeo Look at all that empty space!

@kenshirriff Big, heavy, slow and power hungry, but your data was safer than on a modern SanDisk SSD... 😉

@kenshirriff And it was "as low as" 0.06 cents per byte (0.58 cents in today's dollars) and had an MTBF of 2,000 to 3,000 hours.

@kenshirriff

Smaller and less resource consuming is better?
Whoa, don't tell economists, the car industry or republican politicians?

@kenshirriff I loved Datapoint and Databus!!

@kenshirriff Great computer history thread. Thanks.

@kenshirriff OMG! 729 tape drives! We had 4 of them on our DEC-10 at U Illinois Physics when I was there. I'm amazed that they're still around 50 years later 😮

@kenshirriff I loaded tapes on something like this, back in the 80s. It was fun watching them thread the tape across to the other reel by themselves, and watching the two loops in the vertical channels when it was spinning madly...

@kenshirriff I remember these lamps from my childhood, but don't remember the device. Certainly no computer or telephone.

@kenshirriff Amazing.

@kenshirriff Nicely done

@kenshirriff How is it that you came across it initially? How did it catch your eye?

During a bus hold, the 8086 processor stops using the memory bus and electrically disconnects from the bus by going into "tri-state" mode. This lets an external device take control of the bus and access memory directly. This can be used for high-speed input/output (DMA).

The output pins need high current, so each pin has multiple large transistors in parallel. This diagram shows how long, parallel transistors are created from polysilicon and silicon, and then wired together by the metal layer on top.

@kenshirriff
That brown photo looks like a sepia print of a really well organized area with crops that people could live in.

@kenshirriff

40 pins ought to be enough for everybody

The i960's roots are the iAPX 432, a "micro-mainframe" processor that Intel started in 1976 to revolutionize microprocessors with 32-bit mainframe power in an object-oriented chip. Spoiler: it did not. Far behind schedule, Intel introduced the 8086 processor, a temporary stopgap.

@kenshirriff
Wow fascinating, was there any relation between the i860 and the i960? I remember we were accelerating video decoding in the 90s with a hugely expensive (I thought at the time) dual i860 board.

@kenshirriff very interesting, reading your posts is always a joy :)

keep it up!

We powered up the block that converts a temperature reading to a gear rotation but nothing happened. So I'm reverse-engineering the circuitry to figure out what's gone wrong. Maybe an old capacitor since some of the old capacitors have fungus or corrosion or something.

@kenshirriff I imagine being a caveman and finding this. Sophisticated alien technology from that point of view.

Most 8086 instructions are implemented in microcode, a level of instructions below the familiar machine instructions. But before microcode can run, something called the Group Decode ROM categorizes instructions according to their structure, shown as colors below.

@kenshirriff

Fond memories... When Al Gore invented the internet? I was there.

Consumed the MS DOS 1.1 desk reference cover to cover. Boot stacks for the University coax ethernet. Ugh.

I blew tuition $ on an 8087 (had to get the math chip.)

Fortran! The code and prob data were uploaded by 56kbps modem to the CP6 for calculation. Sometimes those jobs took the whole weekend.

Switched to C.

Ran a Grad student collaborative BBS. 4 telephone lines served about 70 peers.

#history #geek

@kenshirriff
Every time I read one of your pieces I have to re-assess how much of single chip one individual can hold in their head. 😂