Gregory's ServerThis diagram shows the main parts of the 8086 chip; dark labels are affected by HALT. The 8086 is partitioned into an Execution Unit which executes instructions, and a Bus Interface Unit which performs memory operations and preloads instructions into the prefetch queue.
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 The Bus Interface Unit has a lot of flip-flops to manage memory accesses. When a HALT comes in, it finishes any current memory access but new ones are stopped. In particular, the prefetch circuitry is blocked. A special mini-memory-cycle indicates the CPU is in the halt state. The CPU sits in the HALT state until an interrupt or reset signal comes in. This starts a microcode routine to handle the interrupt. The interrupt also blocks the Group Decode ROM from decoding the HLT instruction, ending the HALT state. On the 8086, even something that seems simple like halting the processor has a bunch of complexity and tricky circuitry. For more information, see my latest blog post: https://www.righto.com/2023/01/reverse-engineering-intel-8086.html  @kenshirriff Oh the references to the datapoint and the origin of parity/little endian in the 8086 are fascinating!  |
Most 8086 instructions are implemented in microcode, but some are implemented in logic. The Group Decode ROM starts by categorizing instructions. The red rectangle detects 1-byte-logic instructions that don't use microcode. The yellow rectangle detects the HLT instruction.