Gregory's ServerThe Bus Interface Unit has a lot of flip-flops to manage memory accesses. When a HALT comes in, it finishes any current memory access but new ones are stopped. In particular, the prefetch circuitry is blocked. A special mini-memory-cycle indicates the CPU is in the halt state.
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 On the 8086, even something that seems simple like halting the processor has a bunch of complexity and tricky circuitry. For more information, see my latest blog post: https://www.righto.com/2023/01/reverse-engineering-intel-8086.html  @kenshirriff Oh the references to the datapoint and the origin of parity/little endian in the 8086 are fascinating!  |
The CPU sits in the HALT state until an interrupt or reset signal comes in. This starts a microcode routine to handle the interrupt. The interrupt also blocks the Group Decode ROM from decoding the HLT instruction, ending the HALT state.