Gregory's ServerThe chip uses an I/O block for each pin. The I/O block can be configured as an input or an output, depending on the metal wiring. The chip has 22 I/O blocks but only uses 14 of them. A bond wire is attached to the pad, connecting it to one of the chip's pins. 8/13
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 Manufacturing a chip requires an expensive mask for each layer, maybe 8 layers in a chip like this. But using a gate array, most of the masks can be reused across a product line, with only 2 custom masks for the metal layers. 10/13 A gate array makes each chip more expensive to manufacture because of the wasted die area. But the fixed mask costs are much lower. So a gate array is cheaper when making chips in lower quantities. This made sense for IDT, selling low-volume, high-markup military parts. 11/13 The designers put their initials on the die. There are also mysterious symbols; one looks like the Chinese character "正" with a T below. 12/13 For more on this chip, see my blog post:  @kenshirriff The “正” character is sometimes used as a counter, in the same way we use 4 vertical lines and a slash through it to count to 5. That might be a “7”thing revision of something. https://en.m.wiktionary.org/wiki/正 @kenshirriff is this a precursor to modern FPGAs, in the sense that they mass-produced a chip that would be configured for a specific purpose at a later point? @guenther @kenshirriff Basically yes - It is a Gate Array, just not Field Programmable. And of a rather low complexity. Personally, I'm reminded of the Ferranti ULA (used in the Sinclair hole computers), which is a bit more complex, but also mask programmed. https://en.wikipedia.org/wiki/Gate_array#Development |
Here's my reverse-engineered schematic of one of the chip's two decoders. It takes a two-bit input and activates the corresponding one of the four output lines. Each NAND gate matches one input value. The NOR gates block the output unless the Enable input is active. 9/13