Gregory's ServerHere's an unusual chip, a 7400-series decoder implemented with a gate array. It has over 1500 transistors in orderly rows, but most of them are entirely unused. Why build a chip in such an inefficient way? Let's take a closer look... 1/13
Ken Shirriff
16 comments
Ken Shirriff
Integrated Device Technology was a spinoff from Hewlett-Packard in 1980, building advanced chips. It became part of Renesas in 2018. IDT's logo is pretty cool, combining a chip wafer and calculus. The logo on the die is simplified. 3/13
Ken Shirriff
The chip is implemented as a gate array, a fixed array of transistors that are connected into gates by metal wiring. Each dark rectangle is two transistors. Note most of them are unused. The wiring goes in the empty horizontal channels between the transistors. 4/13
Ken Shirriff
Here's a closeup of a two-transistor block. The five metal contacts can be seen in the photo. The thin polysilicon lines are harder to see; these form the transistor gates. 5/13
Ken Shirriff
Four transistors can be wired into a NAND gate. If either input is high, an NMOS transistor pulls the output low. If both inputs are low, the PMOS transistors pull the output high. Thus, NAND. 6/13
Ken Shirriff
A NOR gate is the opposite. This one is twice as large as the NAND gate, using two transistors in parallel to provide more current. 7/13
Ken Shirriff
The chip uses an I/O block for each pin. The I/O block can be configured as an input or an output, depending on the metal wiring. The chip has 22 I/O blocks but only uses 14 of them. A bond wire is attached to the pad, connecting it to one of the chip's pins. 8/13
Ken Shirriff
Here's my reverse-engineered schematic of one of the chip's two decoders. It takes a two-bit input and activates the corresponding one of the four output lines. Each NAND gate matches one input value. The NOR gates block the output unless the Enable input is active. 9/13
Ken Shirriff
Manufacturing a chip requires an expensive mask for each layer, maybe 8 layers in a chip like this. But using a gate array, most of the masks can be reused across a product line, with only 2 custom masks for the metal layers. 10/13
Ken Shirriff
A gate array makes each chip more expensive to manufacture because of the wasted die area. But the fixed mask costs are much lower. So a gate array is cheaper when making chips in lower quantities. This made sense for IDT, selling low-volume, high-markup military parts. 11/13
Ken Shirriff replied to Ken
The designers put their initials on the die. There are also mysterious symbols; one looks like the Chinese character "正" with a T below. 12/13
Ken Shirriff replied to Ken
For more on this chip, see my blog post: 
jgeorge replied to Ken
@kenshirriff The “正” character is sometimes used as a counter, in the same way we use 4 vertical lines and a slash through it to count to 5. That might be a “7”thing revision of something. https://en.m.wiktionary.org/wiki/正
guenther replied to Ken
@kenshirriff is this a precursor to modern FPGAs, in the sense that they mass-produced a chip that would be configured for a specific purpose at a later point?
Hurgotron ✔ replied to guenther
@guenther @kenshirriff Basically yes - It is a Gate Array, just not Field Programmable. And of a rather low complexity. Personally, I'm reminded of the Ferranti ULA (used in the Sinclair hole computers), which is a bit more complex, but also mask programmed. https://en.wikipedia.org/wiki/Gate_array#Development
DougMerritt (log😅 = 💧log😄)
@kenshirriff I'd forgotten their history though, if in fact I ever knew it. |
This chip was built by Integrated Device Technology (IDT) in 1991 for a military application. It was mounted on a multi-chip module with EEPROMs on either side. 2/13