@thegibson Maybe too esoteric, but I once spent weeks (maybe a month) trying to track down a bug in my verilog code for an FPGA on a new board bringup. I was stressed, the teams was stressed. I was rewriting entire modules and theorizing strange metastability bugs. In the end, the problem was that I had neglected to check a particular box in the configuration for the project so that the generated bitstream would kick the FPGA out of its initialization sequence after it loaded the bitstream. :/