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Marcus Müller

@azonenberg @gsuberland @karotte I'm not very familiar with that, but I think the PHY is relatively similar to modern PCIe, so that would make it relatively uncursed. But the USB4 encapsulate-everything-in-everything has potential for much cursing, will see how that turns out!

5 comments
Lukas

@funkylab

@azonenberg @gsuberland the cursed thing about USB4v2 is that it uses PAM3 on the physical layer.

Andrew Zonenberg

@karotte @funkylab @gsuberland Yes, PAM3 is annoying.

Especially because ~nothing COTS can do PAM3 so there's no hope of speaking it with an FPGA transceiver etc.

jaseg

@azonenberg @karotte @funkylab @gsuberland just out of curiosity, what stops you from configuring the transceivers to PAM-4 and then just not using either the top or the bottom level? Do you get into trouble with level symmetry?

Andrew Zonenberg

@jaseg @karotte @funkylab @gsuberland For TX, I think it would work.

For RX, I think you'd run into problems with asymmetry and the baseline wander correction putting your thresholds in the wrong place.

Andrew Zonenberg

@jaseg @karotte @funkylab @gsuberland (also even PAM4 transceivers are really rare, only like the biggest virtexes have them right now)

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