Gregory's Server@kenshirriff I kinda want to see if you can patch the fdiv bug with a FIB edit now...
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6 comments
 @acsawdey @kenshirriff Yep, that's exactly the question. How extensive the edits are.  @azonenberg @kenshirriff hadn't considered that, yeah maybe it fits but you have to change some large percentage of the logic terms. @acsawdey @kenshirriff The other thing is, you can't FIB a transistor into being. It's easy (ish) to FIB a metal rom in either direction, and to delete a transistor in an active-programmed ROM. But you can't make new ones.  @azonenberg I'd have to study the PLA equations carefully to see if zapping a few transistors would expand the "2" region enough to cover the missing cells. Without looking, I'd give it 50-50 odds of working since it depends on the exact bit patterns. @azonenberg I did some analysis and yes, you could patch the fdiv bug with about 6 FIB edits. By removing transistors, you can expand existing PLA terms to cover the missing table entries. What makes it work is that the unused table entries don't need to be 0, so you have a lot of flexibility. If you needed to change just the bad entries, you'd be stuck. |
@azonenberg @kenshirriff The question I had was, if those 16 entries had been specified correctly in the input to the code that derived the PLA equations ... would that still have fit in the same size (112 rows) of PLA? If not, you'd need more than a FIB to fix this.