Gregory's Serverthe program is written:
wait 1 pin 0
set pins, 1
wait 0 pin 0
set pins, 0
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14 comments
 ahh, they have a 2-flop synchronizer on each input to the pio. but there's a way to disable them on a per-pin basis. i halved the sysclk, so now we have a variability of 13.2ns and a minimum delay of 35.2ns. did a little math and it looks like there is a 2 sysclk delay plus the input propagation delay and output propagation delay. the prop delays total about 8.8ns. hmm so i understand why there is 1 sysclk delay because it takes a cycle to go from the WAIT instruction to the SET instruction. but why 2 sysclk delays? anyway i can overclock to 300MHz sysclk, and now the minimum delay is 15ns. that is 2 cycles of 3.3ns plus 8.4ns propagation through the input and output. argh, i forgot that i put 20MHz BW on the two input channels. anyway, this looks better, the rise time is super fast and the propagation delay is 13.7ns. all right, i'm going to run another 24h aging experiment with 5V on the unpowered pin. let's see how it does. i'll do the measurements at 150MHz. my suspicion is that hot carrier injection could increase the propagation delay of the input, but we shall see. i could dig into this some more, but for now, it looks like the RP2350 is 5V tolerant. i didn't see any evidence of HCI or metal migration. these aren't exhaustive tests since i didn't do them over the full supply voltage and temperature range, so i wouldn't use it for 5V tolerance in a commercial project, but this should be fine for hobby projects.  @tubetime Sorry if you already said it and I lost the info, but did you test only on FT pins or also no non FT pins?  @tubetime now do the RP2040, that one is a bit more of an open question 😅 |
and the propagation delay data is in. i increased persistence. as expected, the variation in the delay is approximately 6.6ns which is one sysclk cycle. this is the synchronization time. minimum delay is 36.4ns which seems long--i'm going to try and figure out why.