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Ken Shirriff

Getting back to the 8088's system bus, the bus uses a four-step sequence of operations to access memory or I/O devices. These steps are called T-states: T1, T2, T3, and T4. A read operation provides the address during T1 and receives the data during T3. 6/8

A timing diagram showing the four states of the 8088's bus cycle: T1, T2, T3, and T4.
28 April at 15:37 | Open on oldbytes.space
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Ken Shirriff

A complicated state machine moves the processor through the T-states. This diagram shows the location of the bus state machine circuitry on the die of the 8088 processor. Back in 1979, just a few flip-flops and logic gates occupied a substantial area on the die. 7/8

A closeup of the die of the 8088 processor showing the flip-flops for the various bus states as well as the logic that computes the states.
28 April at 15:37 | Open on oldbytes.space
Ken Shirriff

The 8088's bus state machine is too complicated to explain here. Instead, see my blog post for lots of diagrams and schematics: righto.com/2024/04/intel-8088- 8/8

28 April at 15:37 | Open on oldbytes.space
Chartreuse

@kenshirriff If anything that also shows just how optimized the rest is to not fit all the functionality in the rest of the space, especially with the decode logic taking up so much too.

28 April at 21:52 | Open on social.restless.systems
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