Gregory's Serveraccording to the datasheet, it is an NMOS device, and it requires three power supply voltages: 5V, 12V (!) and -8V (!!). the 5V supply is for the IO, the 12V supply is for the core voltage, and the -8V supply is the substrate bias.
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 i've added some 74-series latches to demux the address lines from the data lines. to get it to fit in a 40-pin package, the address bus is muxed with the data bus. the LEDs indicate the current address, and they count up! the program counter is counting. the next step is to add some program memory. it is all 16 bit, so i am using two 8 bit flash memory chips. i guess i should write a program. there is an assembler that supports this architecture (http://john.ccac.rwth-aachen.de:8000/as/) but i'll get that working later. for now i will just write it in machine code. and we have a blinking LED! this is being driven from one of the 4 flag outputs on the CPU. the bus timing looks like this. the top trace is the clock, then there is NADS, IDS (input data strobe), and finally the F11 output (which is driving the LED). i cheated and slowed the clock down for the video so you could see it blink.  @tubetime +12V was common for early NMOS, before depletion loads, but usually Vgg (before substrate bias generators) was -5V. Oddball Vgg voltages were sometimes specified in order to have better performance or better margins. A few chips, even in production (!) had a Vgg value determined by production test hand-written on the IC package! |
using the resistors, i wired the 16 data lines to the NOP instruction. and the CPU appears to be running!
on top is the clock trace (12V logic!) and in the middle is the IDS (input data strobe), and on the bottom is the NADS (address strobe). yes, the chip has NADS.