Gregory's ServerInstructions for the 8086 processor specify registers through 3 bits in the opcode or following byte. This is expanded to a 5-bit code to support 16-bit registers (red), 8-bit registers (blue), segment registers (green), and special internal registers.
|
7 comments
 The 8086 processor uses microcode, implementing most machine instructions through a sequence of simpler micro-instructions. These micro-instructions can use the M and N registers to access registers specified in the instruction. This microcode exchanges two registers. Each micro-instruction includes a register move between a source and destination register. The micro-instruction can specify the 5-bit code directly, or use the M and N registers for indirection. This way, microcode doesn't need to know which registers an instruction specifies. This system is a bit complicated, but gives the 8086 a lot of flexibility for specifying which registers to use. For more information, see my blog post https://www.righto.com/2023/03/8086-register-codes.html  @kenshirriff awesome! so what does this processor has to do with the 80186, 80286 and so on? it is the name architecture/instruction sets but more transistors instead? or completely different? @santiago The 80186, 80286, Pentium, etc. are improvements to the 8086, adding more instructions and features and lots more transistors but keeping binary compatibility. Modern x86 chips can still run 8086 code (but only in virtual real mode). @kenshirriff I remember as a kid, playing DOS gamen with a DEC PC, cannot remember the model, late 80s. Sure ut was a 186 or 286 at most. Miss those good old days. Last week i got a Texas Instruments Voyage 200 with a Motorola 68k processor at 12MHz... I think that those fan less and even cooler-less processors, were the top, everything with a fan+cooler after, was all the way down. Thanks for sharing! |
To provide a level of indirection, the 5-bit register specifications are held in the internal M and N registers. This closeup die photo shows how the M and N registers are implemented on the chip.