A novel concept for a fully digital particle detector,...

A novel concept for a fully digital particle detector, G. Casse et, al. Journal of Instrumentation. https://iopscience.iop.org/article/10.1088/1748-0221/17/04/P04010

Make an SRAM chip that is very vulnerable to Single Event Upsets from radiation, so you can detect particles by looking for bitflips :blobcatgiggle: I think this is not the first time this trick is used. "It's not a bug, it's a feature!" #electronics

2.1 The digital sensor concept

Memory cells are digital circuits with two selectable states (0 and 1) used to store a single bit of information. The typical layout of the widely used static random access memory (SRAM) is shown in figure 1a. Four central transistors (Mn1, Mp1, Mn2, Mp2) form two cross-coupled inverters. The operations are performed by setting the write line (WL) that controls the gate of transistors Mn3 and Mn4. The bit lines BTL (nBTL) is driven high (low) by the inverter circuit. For writing, a logic '1' or '0' is applied to the bit lines, the WL is asserted and the set value is stored. Memories are subjected to occasional, undesired state changes induced by crossing ionising particles. These events are called single or multiple event upset (SEU or MEU) depending on the number of digital nodes affected [7]. They cause problems (soft errors) in electronics with high transistor density. Digital circuits are designed to be robust against these, by implementing temporal or spatial redundancy, dummy structures or other mechanisms for correcting their occurrence. Thanks to these measures, SEUs occur at very low rates in modern electronics. Instead, we want a digital device with very high probability of a state change induced by crossing ionising particles.

Figure 2. schematics of implemented digital sensor (Dsens) cells: a) circuit level schematic of the improved Dsen1 cell; b) cell layout of the improved Dsen1 cell using UMC 65 nm.

Like 26 Jul 2022 at 4:32 | Open on cybre.space