@karotte @leah in practice: many of the very established UART controller IP cores simply have state machine bugs – Cadence, things that ended up in FTDI converters, Zynqs, …
UART also is extremely cursed in concept, with the idea that sample something happening on a physically noisy channel and then go ahead with nothing but at most a single parity bit and act as if it's reliable – and that although you're not even sure where the symbol transitions happened. UART is very very cursed.