@kenshirriff As stated by Wikipedia:

In order to improve the speed of floating-point division calculations [...] Intel opted to replace the shift-and-subtract division algorithm with the Sweeney, Robertson, and Tocher (SRT) algorithm. [...] It is implemented using a programmable logic array with 2,048 cells, [...] When the original array for the Pentium was compiled, five values were not correctly sent to the equipment that etches the arrays into the chips – thus five of the array cells contained zero when they should have contained +2.

As a result, calculations that rely on these five cells acquire errors; these errors can accumulate repeatedly owing to the recursive nature of the SRT algorithm.

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First time I've actually seen pictures of the relevant parts of the die though. Amazing!