Gregory's Serverthis is an effect of the precharge mosfet. the clock signal goes to the gate, the drain goes to 5V, and the source goes to the data bus bit. the idea is that when the clock goes high, the bit gets charged up (to the clock pulse voltage minus the threshold voltage). when the clock goes low, the mosfet turns off, and the data bit remains charged.
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 I've replaced the precharge mosfet with an analog switch chip -- one of those little circuit boards. and look: the glitch is gone, and we've got a clean signal now. the rising edge looks much cleaner as well. (we're looking at channel 2, purple)  @tubetime Was gonna say cuz that rising edge on yellow looks hella analog 😃 That said I like how the scope is labelling the voltages on the right edge.My Rigol doesn't do that, it seems like a reasonable upgrade. |
in practice, due to the gate to source capacitance (Cgs) the falling edge of the clock couples into the data bus bit. years ago I added bus capacitance which mitigates this somewhat. I've come up with a better solution.