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10 comments
Tube❄️Time

routed (except for a few RAS and CAS lines). i also have the schematic, but it needs cleanup work.

Tube❄️Time

dumped the PROM. it seems to be part of the address decoding process or memory mapping.

Tube❄️Time

so this board looks like it does both XMS (extended memory) and EMS (expanded memory). expanded memory is banked and uses a 64K (iirc) window to access it.

William D. Jones replied to Tube❄️Time

@tubetime Ahhh, so it's like the AST RAMpage 286 :D!

Tube❄️Time replied to Tube❄️Time

well crap, this board appears to be a clone of the Intel Above Board Plus 8 card. it sure looks the same!

Tube❄️Time replied to Tube❄️Time

yeah sure looks identical. welp, now we know how it works, lol.

Tube❄️Time replied to Tube❄️Time

OK, here are the KiCad files. it's not really a fab-able design because there are still DRC errors, but at least the schematic is useful.

github.com/schlae/XebecAboveBo

root42 replied to Tube❄️Time

@tubetime but has it ever been reverse engineered before…? That would be a bummer. But if not: success!

Keelan

@tubetime how do you go from PCB layout to schematic? When I did this, I ended up tracing the PCB in a CAD package, the writing a thing that analyzed the lines and spit out a netlist. I then learned that while many tools exist to convert schematics to netlists, I couldn’t find much to go the other way ‘round.

Tube❄️Time

@keelan i'm running a trace in layout, seeing where it goes, then creating the connectivity in the schematic and pushing it to layout to create the connection.

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